-- Adder Architecture
-- Chang Lan, <changlan9@gmail.com>
-- 11/9/2011

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

architecture behave of adder is

begin
    process(a, b)
        -- declare variables
        variable a_uns : unsigned(width-1 downto 0);
        variable b_uns : unsigned(width-1 downto 0);
		variable r_uns : unsigned(width-1 downto 0);
        
    begin
        a_uns := unsigned(a);
        b_uns := unsigned(b);
        r_uns := a_uns + b_uns;

        -- assign variables to output signals
        result <= std_ulogic_vector(r_uns);
        
    end process;

end behave;
